Usage
The following registers are provided for altering the behavior of the exerciser. These are similar to the "Set" expressions, except that they provide more direct access to the FPGA Registers.
Syntax
The following registers can be set using the SetRegister function:
SetRegister(<register_address>, <value>)
Example
SetRegister ( 0x0030, 0x4)
Used to set the value "4" in the TRAINER_RESET register.
Table of Registers
|
Name |
Address |
Comment |
|
SKP_TIMER |
0x0014 |
See below |
|
SKP_TIMER_SSP |
0x0028 |
See below |
|
TRAINER_RESET |
0x0030 |
0x0 : Remove PHY layer (Including LTSSM) from reset mode 0x010000000 : Keep PHY layer (Including LTSSM) in reset mode 0x4 : This will direct LTSSM from Polling to HotReset, the first time LTSSM passes through Polling state. 0x01800000 : Phy layer in reset mode, as well as trainer function |
|
WARM_RESET_CONTROL1 |
0x0034 |
See below |
|
PM_ACCEPT_MODE |
0x0064 |
See below |
|
CORRUPT_LC |
0x0114 |
See below |
|
CORRUPT_LMP |
0x0118 |
See below |
|
CORRUPT_SHP_FRAMING |
0x0124 |
See below |
|
CORRUPT_SDP_FRAMING |
0x0128 |
See below |
|
CORRUPT_END_FRAMING |
0x012C |
See below |
|
CORRUPT_SLC_FRAMING |
0x013C |
See below |
|
DELAY_LAU |
0x015C |
See below |
|
Insert K-Sym Error (LC and HP) |
0x0160 |
See below |
|
|
0x0200 |
See below |
|
LTSSM_U3EXIT_CONTROL |
0x0214 |
See below |
|
LTSSM_HOT_RESET_TIME |
0x0218 |
See below |
|
LTSSM_RXDETECT_CONTROL |
0x021C |
User can insert a delay between U1 entry and the first Ping in U1 state. Each value will be multiplied by 8ns in hardware. For example, to insert 100ms delay before sending the first ping in U1 user should write this value 0x0BEBC20 in this register. |
|
LTSSM_DELAY_BEFORE_U1 |
0x0220 |
Count of 8ns intervals to configure wait before U1 periods start |
|
GENERATE_LFPS_COMMAND |
0x0340 |
See below |
|
LFPS_SCD_TREPEAT_0 |
0x324 |
See below |
|
LFPS_SCD_TREPEAT_1 |
0x328 |
See below |
|
LFPS_PWM |
0x32C |
See below |
|
LFPS_LBPM_Logic_0 |
0x330 |
See below |
|
LFPS_LBPM_Logic_1 |
0x334 |
See below |
Registers
SKP_TIMER
(Offset in the Register Area: 0x0014)
Controls the behavior of SKP generator. The SKP generator can work automatically or based on the interval time programmed by user through this command. In addition, it permits to control the number of pending SKP requests before trying to send them.
|
MSB |
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LSB |
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Timer |
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|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Reserved |
M.A |
TS1 |
Pnd Cnt |
Reserved |
Auto |
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|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
|
0 |
AUTO 0: Use the interval time programmed in Interval field, 1: Use automatic timing for SKP intervals |
|
7:1 |
Reserved, filled by 0 |
|
9:8 |
Pnd Cnt Number of pending SKP requests before sending a SKP sequence. 0: Don’t keep any pending SKP request, send them out whenever there is any. 1: Keep 1 request. Send SKP sequence when there are at least 2 requests. 2: Keep 2 requests. Send SKP sequence when there are at least 3 requests. 3: Keep 3 requests. Send SKP sequence when there are 4 requests. |
|
10 |
TS1 1: Send SKP sequence before first TS1 OrderedSet in Polling.Active and Recovery.Active 0: Normal behavior, send SKP sequences on the schedule during TS1 transmission; no need to send a SKP sequence before TS1s |
|
11 |
Misaligned Interval When this bit is set the interval is misaligned. Pending count = 0 => interval = 353 Pending count = 1 => interval = 707 Pending count = 2 => interval = 1061 Pending count = 3 => interval = 1215 |
|
15:12 |
Reserved, filled by 0 |
|
31:16 |
Interval User defined interval time in terms of 8ns units. HW will meet it with the best possible accuracy if AUTO bit is not set. |
SKP_TIMER_SSP
(Offset in the Register Area: 0x0028)
Controls the behavior of SKP generator in SSP mode. Exerciser tries to send a “Total SKP OS Count” of SKP ordered set in every period of “Interval+1” blocks. In each period, Exerciser sends “Max Burst SKP OS” back-back with no blocks in between, and sends the rest of SKP counts with at least one block in between.
Each sent SKP OS contains “Variable SKIP Counter” symbols of SKP followed by one SKPEND symbol and the three bytes of LFSR as defined by spec.
Here are two examples for clarity:
If Variable SKIP Counter = 4, Total SKP OS Count = 1, Max Burst SKP OS Count = 1, Interval = 40, the result is:
-
40 Blocks of non-SKP
-
One Block of SKP containing 4xSKP, SKPEND, LFSR
If Variable SKIP Counter = 36, Total SKP OS Count = 4, Max Burst SKP OS Count = 3, Interval = 163, the result is:
-
159 Blocks of non-SKP
-
Three Block of SKP containing 36xSKP, SKPEND, LFSR
-
One block of non-SKP
-
One Block of SKP containing 36xSKP, SKPEND, LFSR
|
MSB |
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LSB |
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|
Interval |
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|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Max Burst SKP OS Count |
Total SKP OS Count |
Rsrv |
Variable SKIP Counter |
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|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
6:0 |
Variable SKIP Counter This valueshows how many SKP symbols should be sent in a single SKP OS. The default value is 12. |
RW |
|
7 |
Reserved, fill by 0 |
RO |
|
11:8 |
Total SKP OS Count This value shows how many accumulated SKP OS should be sent every Interval. The default value is 1. |
RW |
|
15:12 |
Max Burst SKP OS Count This value shows how many SKP OS should be sent in burst, without any other 132 bit block in between of them. This value should always be less than or equal to Total SKP OS Count. The default value is 1. |
RW |
|
31:16 |
Interval This field defines the number of blocks (data/control) between the first SKP OS of each burst and the first SKP OS of next burst. The default value is 40. |
RW |
FLOWCONTROL_SETTING
(Offset in the Register Area: 0x0018)
Controls the Link layer handshake mechanisms including LGOOD/LBAD and LCRD generation and detection.
|
MSB |
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LSB |
||
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Reserved |
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|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Reserved |
LCRD Gen Dis |
LGOOD Gen Dis |
LCRD Det Dis |
LGOOD Det Dis |
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|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
0 |
LGOOD Detection Disable 0: Trainer will check and wait for received LGOOD/LBAD to decide about retransmission. 1: LGOOD/LBAD detection is disabled, so any packet transmitted will be instantly purged from Tx buffer. |
RW |
|
1 |
LCRD Detection Disable 0: Trainer will wait for received LCRD to count up the number of available credits in the Rx buffer of DUT. 1: Trainer assumes that DUT will have always enough credits for receiving packets. |
RW |
|
2 |
LGOOD Generation Disable 0: Trainer will check the validity and integrity of received packets and will respond it by generating appropriate LGOOD or LBAD. 1: Trainer will ignore any error check and will assume all received packets as good packets, without sending LGOOD. |
RW |
|
3 |
LCRD Generation Disable 0: Trainer will check the available space in Rx buffer to store received packet and send appropriate LCRD when the corresponding Rx buffer becomes empty. 1: Trainer will ignore Rx buffer space check and also will not respond by LCRD. |
RW |
|
4 |
LCRD order during advertisement 0: Trainersends LCRDi_x in Alphabetic order (i.e LCRD1_A, LCRD2_A, LCRD1_B, LCRD2_B, LCRD1_C, LCRD2_C, LCRD1_D, LCRD2_D) 1: Trainersends LCRDi_x in Numerical order (i.e. LCRD1_A, LCRD1_B, LCRD1_C, LCRD1_D, LCRD2_A, LCRD2_B, LCRD2_C, LCRD2_D) |
RW |
|
31:5 |
Reserved, filled by 0 |
RO |
WARM_RESET_CONTROL1
(Offset in the Register Area: 0x0034)
Controls Warm Reset issued by the SetLinkState command. A Warm Reset is normally transmitted when LTSSM driven to
1) RX DETECT or
2) POLLING or
3) U0 when current LTSSM state is not U0, U1, U2 or U3
|
MSB |
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|
LSB |
||
|
Reserved |
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|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Reserved |
WRLSC2 EN |
WRLSC EN |
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|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
0 |
WRLSC EN 0: Warm Reset is not issued by Host when directed by SetLinkState Command (default in BE). Applies when current LTSSM state is DISABLE or POWER_ON. 1: No effect. |
RW |
|
1 |
WRLSC2 EN 0: No effect (default in BE). 1: Warm Reset not issued by Host when directed by SetLinkState Command. Applies when current LTSSM state is U0, U1, U2 or U3 and LTSSM is not driven to U0. |
RW |
|
31:2 |
Reserved, filled by 0 |
RO |
PM_ACCEPT_MODE
(Offset in the Register Area: 0x0064)
Controls the behavior of the device in response to Power Management states entry request (LGO_Un).
|
MSB |
|
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|
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|
LSB |
||
|
Reserved |
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|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Reserved |
DROP |
Auto |
AU3 |
AU2 |
AU1 |
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|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
0 |
AU1 0: Reject the request of entering U1 by sending LXU, 1: Accept the request of entering U1 by sending LAU |
RW |
|
1 |
AU2 0: Reject the request of entering U2 by sending LXU, 1: Accept the request of entering U2 by sending LAU |
RW |
|
2 |
AU3 0: Reject the request of entering U3 by sending LXU, 1: Accept the request of entering U3 by sending LAU* |
RW |
|
3 |
AUTO 0: Reply to the LGO_Un according to the bits 0 to 2. 1: Reply to the LGO_Un based on the configured value through LMPs. |
RW |
|
4 |
LAU Drop 0: Normal 1: Drop any LAU. |
RW |
|
31:4 |
Reserved, filled by 0 |
RO |
* It seems problematic because according to spec, LGO_U3 shall be replied just by a LAU.
CORRUPT_LC
(Offset in the Register Area: 0x0114)
This command forces the link layer to send LCs with wrong CRC-5. It will effect on any LC outgoing from the link layer until the command is stopped automatically or manually.
|
MSB |
|
|
|
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|
LSB |
||
|
Reserved |
LC Part |
CRC Part |
LC Type |
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|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Count |
Reserved |
ONCE |
Reserved |
INF |
EN |
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|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
0 |
EN 0: Disable (stop error injection), 1: Enable (run error injection) This bit will be cleared automatically when the INF bit is not set and the Count value is reached down to zero. |
RW |
|
1 |
INF 0: Run the command for the number of times specified in the Count field, 1: Run the command for infinite times until the EN bit is set. |
RW |
|
3:2 |
Reserved, filled by 0 |
RO |
|
4 |
ONCE This bit shows that the error has been injected at least once from the last time EN has been set. It will be cleared whenever a value 1 is written to EN. |
RO |
|
7:5 |
Reserved, filled by 0 |
RO |
|
15:8 |
Count Number of times the error should be injected if the MODE is 1. When read, it shows number of times remained yet to finish the requested count. |
RW |
|
19:16 |
LC Type This field determines which LC types should be affected by this command. 0: All LCs (LGOOD_x and LCRD_x) 1: Just LCRD 2: Just LGO_Ux (In fact Just LGO_U1) Others: Reserved for future use. |
RW |
|
21:20 |
CRC Part This field defines CRC in which part of LC should be corrupted. 00: no of them 01: first part 10: second part 11: both parts |
RW |
|
23:22 |
LC Part This field defines LC data in which part of LC should be corrupted. 00: no of them 01: first part 10: second part 11: both parts |
RW |
|
31:24 |
Reserved, filled by 0 |
RO |
CORRUPT_LMP
(Offset in the Register Area: 0x0118)
This command contains all applicable error injections for the LMP packets.
|
MSB |
|
|
|
|
|
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|
|
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|
LSB |
||
|
Reserved |
WAT |
SEC |
CFG |
CAP |
HSN |
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|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
CRC-16 |
CRC-5 |
Reserved |
DONE |
Reserved |
INF |
EN |
|||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
0 |
EN 0: Disable (stop error injection), 1: Enable (run error injection) This bit will be cleared automatically when the INF bit is not set and requested error injection is done. |
RW |
|
1 |
INF 0: Run the command once, on the first series of LMP generation, 1: Run the command until the EN bit is set. |
RW |
|
3:2 |
Reserved, filled by 0 |
RO |
|
4 |
DONE This bit shows that the error has been injected at least once from the last time EN has been set. It will be cleared whenever a value 1 is written to EN. |
RO |
|
7:5 |
Reserved, filled by 0 |
RO |
|
11:8 |
CRC-5 Bit 0 (bit 8 of whole DW); 1: Disable auto CRC-5 calculation Bit 1 (bit 9 of whole DW); 0: Run for limited number of times specified in register PKT_CRC5_ERROR_COUNT, 1: Run for infinite number of times until the Bit 0 is set. Bits 3:2 (bits 11:10 of whole DW); reserved for future. |
RW |
|
15:12 |
CRC-16 Bit 0 (bit 12 of whole DW); 1: Disable auto CRC-16 calculation Bit 1 (bit 13 of whole DW); 0: Run for limited number of time specified in PKT_CRC16_ERROR_COUNT register, 1: Run for infinite number of time until the Bit 0 is set. Bits 3:2 (bits 15:14 of whole DW); reserved for future. |
RW |
|
19:16 |
HSN (Header Sequence Number) Bit 0 (bit 16 of whole DW); 1: Disable auto LCW Header Sequence Number manipulation Bit 1 (bit 17 of whole DW); 0: Run for limited number of time specified in PKT_SEQ_ERROR_COUNT register, 1: Run for infinite number of time until the Bit 0 is set. Bits 3:2 (bits 19:18 of whole DW); reserved for future. |
RW |
|
20 |
CAP Don’t send Port Capability LMP upon entering U0 |
RW |
|
21 |
CFG Don’t send Port Configuration LMP (or Port Configuration Response LMP) upon entering U0 |
RW |
|
22 |
SEC insert error setting only on second LMP |
RW |
|
23 |
WAT Wait for Port capability for both host and device mode |
RW |
|
31:24 |
Reserved, filled by 0 |
RO |
CORRUPT_SHP_FRAMING
(Offset in the Register Area: 0x0124)
This command forces the link layer to send Header Packet with one invalid symbol in SHP framing sequence. Any symbol of the framing sequence can be selected (using Bitmap field) to be replaced by specified symbol (K and 8b fields).
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
8b |
K |
USR |
Reserved |
Bitmap |
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|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Count |
Reserved |
ONCE |
Reserved |
INF |
EN |
||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
0 |
EN 0: Disable (stop error injection), 1: Enable (run error injection) This bit will be cleared automatically when the INF bit is not set and the Count value is reached down to zero. |
RW |
|
1 |
INF 0: Run the command for the number of times specified in the Count field, 1: Run the command for infinite times until the EN bit is set. |
RW |
|
3:2 |
Reserved, filled by 0 |
RO |
|
4 |
ONCE This bit shows that the error has been injected at least once from the last time EN has been set. It will be cleared whenever a value 1 is written to EN. |
RO |
|
7:5 |
Reserved, filled by 0 |
RO |
|
15:8 |
Count Number of times the error should be injected if the MODE is 1. When read, it shows number of times remained yet to finish the requested count. |
RW |
|
19:16 |
Bitmap This field determines which symbols in the framing sequence should be corrupted. Bit 16 corresponds to first framing symbol in the sequence and bit 19 corresponds to EPF. SW should always write a non-zero value into this field, otherwise, it will not inject any error. |
RW |
|
21:20 |
Reserved, filled by 0 |
RO |
|
22 |
USR 1: Use user-defined pattern 0: Use default pattern |
RW |
|
23 |
K 0: D-Code, 1: K-Code |
RW |
|
31:24 |
8b 8-bit code of substituting pattern |
RW |
CORRUPT_SDP_FRAMING
(Offset in the Register Area: 0x0128)
This command forces the link layer to send first Data Packet with some invalid symbol in SDP framing sequence. Any symbol of the framing sequence can be selected (using Bitmap field) to be replaced by specified symbol (K and 8b fields).
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
8b |
K |
USR |
Reserved |
Bitmap |
|||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Count |
Reserved |
ONCE |
Reserved |
INF |
EN |
||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
0 |
EN 0: Disable (stop error injection), 1: Enable (run error injection) This bit will be cleared automatically when the INF bit is not set and the Count value is reached down to zero. |
RW |
|
1 |
INF 0: Run the command for the number of times specified in the Count field, 1: Run the command for infinite times until the EN bit is set. |
RW |
|
3:2 |
Reserved, filled by 0 |
RO |
|
4 |
ONCE This bit shows that the error has been injected at least once from the last time EN has been set. It will be cleared whenever a value 1 is written to EN. |
RO |
|
7:5 |
Reserved, filled by 0 |
RO |
|
15:8 |
Count Number of times the error should be injected if the MODE is 1. When read, it shows number of times remained yet to finish the requested count. |
RW |
|
19:16 |
Bitmap This field determines which symbols in the framing sequence should be corrupted. Bit 16 corresponds to first framing symbol in the sequence and bit 19 corresponds to EPF. SW should always write a non-zero value into this field, otherwise, it will not inject any error. |
RW |
|
21:20 |
Reserved, filled by 0 |
RO |
|
22 |
USR 1: Use user-defined pattern 0: Use default pattern |
RW |
|
23 |
K 0: D-Code, 1: K-Code |
RW |
|
31:24 |
8b 8-bit code of substituting pattern |
RW |
CORRUPT_END_FRAMING
(Offset in the Register Area: 0x012C)
This command forces the link layer to send first Data Packet with one invalid symbol in END framing sequence.Any symbol of the framing sequence can be selected (using Bitmap field) to be replaced by specified symbol (K and 8b fields).
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
8b |
K |
USR |
Reserved |
Bitmap |
|||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Count |
Reserved |
ONCE |
Reserved |
INF |
EN |
||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
0 |
EN 0: Disable (stop error injection), 1: Enable (run error injection) This bit will be cleared automatically when the INF bit is not set and the Count value is reached down to zero. |
RW |
|
1 |
INF 0: Run the command for the number of times specified in the Count field, 1: Run the command for infinite times until the EN bit is set. |
RW |
|
3:2 |
Reserved, filled by 0 |
RO |
|
4 |
ONCE This bit shows that the error has been injected at least once from the last time EN has been set. It will be cleared whenever a value 1 is written to EN. |
RO |
|
7:5 |
Reserved, filled by 0 |
RO |
|
15:8 |
Count Number of times the error should be injected if the MODE is 1. When read, it shows number of times remained yet to finish the requested count. |
RW |
|
19:16 |
Bitmap This field determines which symbols in the framing sequence should be corrupted. Bit 16 corresponds to first framing symbol in the sequence and bit 19 corresponds to EPF. SW should always write a non-zero value into this field, otherwise, it will not inject any error. |
RW |
|
21:20 |
Reserved, filled by 0 |
RO |
|
22 |
USR 1: Use user-defined pattern 0: Use default pattern |
RW |
|
23 |
K 0: D-Code, 1: K-Code |
RW |
|
31:24 |
8b 8-bit code of substituting pattern |
RW |
CORRUPT_SLC_FRAMING
(Offset in the Register Area: 0x013C)
This command forces the link layer to send upcoming Link Command with one invalid symbol in SLC framing sequence. Any symbol of the framing sequence can be selected (using Bitmap field) to be replaced by specified symbol (K and 8b fields).
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
8b |
K |
USR |
LC Type |
Bitmap |
|||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Count |
Reserved |
ONCE |
Reserved |
INF |
EN |
||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
0 |
EN 0: Disable (stop error injection), 1: Enable (run error injection) This bit will be cleared automatically when the INF bit is not set and the Count value is reached down to zero. |
RW |
|
1 |
INF 0: Run the command for the number of times specified in the Count field, 1: Run the command for infinite times until the EN bit is set. |
RW |
|
3:2 |
Reserved, filled by 0 |
RO |
|
4 |
ONCE This bit shows that the error has been injected at least once from the last time EN has been set. It will be cleared whenever a value 1 is written to EN. |
RO |
|
7:5 |
Reserved, filled by 0 |
RO |
|
15:8 |
Count Number of times the error should be injected if the MODE is 1. When read, it shows number of times remained yet to finish the requested count. |
RW |
|
19:16 |
Bitmap This field determines which symbols in the framing sequence should be corrupted. Bit 16 corresponds to first framing symbol in the sequence and bit 19 corresponds to EPF. SW should always write a non-zero value into this field, otherwise, it will not inject any error. |
RW |
|
21:20 |
LC Type This field determines which LC types should be affected by this command. 0: All LCs 1: Just LCRD Others: Reserved for future use. |
RW |
|
22 |
USR 1: Use user-defined pattern 0: Use default pattern |
RW |
|
23 |
K 0: D-Code, 1: K-Code |
RW |
|
31:24 |
8b 8-bit code of substituting pattern |
RW |
PKT_CRC5_ERROR_COUNT
(Offset in the Register Area: 0x0130)
Sets the number of repetition of CRC-5 error injection on a packet if this error injection is enabled in its descriptor. Any packet with CRC-5 auto-calculation disabled in its descriptor will be sent for the count number specified in this register without calculating the CRC-5 automatically.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Reserved |
|||||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Reserved |
Count |
||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
3:0 |
COUNT Specifies number of times the relevant error should be repeated on a transmitting packet, if the corresponding error injection is requested on that packet through its descriptor. |
RW |
|
31:4 |
Reserved, filled by 0 |
RO |
PKT_CRC16_ERROR_COUNT
(Offset in the Register Area: 0x0134)
Sets the number of repetition of CRC-16 error injection on a packet if this error injection is enabled in its descriptor. Any packet with CRC-16 auto-calculation disabled in its descriptor will be sent for the count number specified in this register without calculating the CRC-16 automatically.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Reserved |
|||||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Reserved |
Count |
||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
3:0 |
COUNT Specifies number of times the relevant error should be repeated on a transmitting packet, if the corresponding error injection is requested on that packet through its descriptor. |
RW |
|
31:4 |
Reserved, filled by 0 |
RO |
PKT_SEQ_ERROR_COUNT
(Offset in the Register Area: 0x0138)
Sets the number of repetition of LCW Header Sequence Number error injection on a packet if this error injection is enabled in its descriptor.
Any packet with Header Sequence Number auto-manipulation disabled in its descriptor will be sent for the count number specified in this register without replacing its Header Sequence Number automatically.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Reserved |
|||||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Reserved |
Count |
||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
3:0 |
COUNT Specifies number of times the relevant error should be repeated on a transmitting packet, if the corresponding error injection is requested on that packet through its descriptor. |
RW |
|
31:4 |
Reserved, filled by 0 |
RO |
DELAY_LAU
(Offset in the Register Area: 0x015C)
This command adds a specific delay to the response time of LAU.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Delay |
|||||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Count |
Reserved |
ONCE |
Reserved |
INF |
EN |
||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
0 |
EN 0: Disable (stop error injection), 1: Enable (run error injection) This bit will be cleared automatically when the INF bit is not set and the Count value is reached down to zero. |
RW |
|
1 |
INF 0: Run the command for the number of times specified in the Count field, 1: Run the command for infinite times until the EN bit is set. |
RW |
|
3:2 |
Reserved, filled by 0 |
RO |
|
4 |
ONCE This bit shows that the error has been injected at least once from the last time EN has been set. It will be cleared whenever a value 1 is written to EN. |
RO |
|
7:5 |
Reserved, filled by 0 |
RO |
|
15:8 |
Count Number of times the error should be injected if the MODE is 1. When read, it shows number of times remained yet to finish the requested count. |
RW |
|
31:16 |
Delay This field contains the delay time value. Granularity of the delay time is 100ns, i.e. each unit in this field is equal to 100ns. |
RW |
Insert K-Sym Error (LC and HP)
(Offset in the Register Area: 0x0160)
This command inserts a K-sym in LC data and HP data.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Symbol |
Reserved |
LOC |
LC |
HP |
|||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Count |
Reserved |
ONCE |
Reserved |
INF |
EN |
||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
0 |
EN 0: Disable (stop error injection), 1: Enable (run error injection) This bit will be cleared automatically when the INF bit is not set and the Count value is reached down to zero. |
RW |
|
1 |
INF 0: Run the command for the number of times specified in the Count field, 1: Run the command for infinite times until the EN bit is set. |
RW |
|
3:2 |
Reserved, filled by 0 |
RO |
|
4 |
ONCE This bit shows that the error has been injected at least once from the last time EN has been set. It will be cleared whenever a value 1 is written to EN. |
RO |
|
7:5 |
Reserved, filled by 0 |
RO |
|
15:8 |
Count Number of times the error should be injected if the MODE is 1. When read, it shows number of times remained yet to finish the requested count. |
RW |
|
16 |
HP This bit enables K-symbol injection into Header Packet data. 0: Disabled 1: Enabled |
RW |
|
17 |
LC This bit enables K-symbol injection into Link Command data. 0: Disabled 1: Enabled |
RW |
|
21:18 |
LOC This 4-bit field determines the byte number of the HP or LC on which the K-symbol should be injected. For LC, just lower 2 bits are valid (locations from 0 to 3). For HP, all bits are meaningful (locations from 0 to 15). |
RW |
|
23:22 |
Reserved, filled by 0 |
RO |
|
31:24 |
Symbol This 8-bit field indicates the 8b encoding of the requested K-symbol for injection. |
RW |
LTSSM_SETTING
(Offset in the Register Area: 0x0200)
Controls the LTSSM operation through enabling/disabling of different handshakes. Can disable the Polling.LFPS handshake in LTSSM and cause to jump from RX_Detect to Polling.Active directly. Can disable any of the handshakes required in different steps of link training and force the LTSSM to move forward through training sub-states after sending appropriate number of TS OrderedSets.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Reserved |
|||||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Reserved |
RxDet |
HRST |
U3EX |
RTW |
BRE |
Idle |
TS2 |
TS1 |
TSEQ |
LFPS |
|||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
0 |
LFPS 0: Polling.LFPS is enabled, 1: Polling.LFPS detection is disabled. Default value is 0. |
RW |
|
1 |
TSEQ 0: LTSSM will send up to 65536 TSEQ OrderedSets and stops sending upon reception of TS1, 1: LTSSM will send specified number of TSEQ OrderedSets Default value is 0. |
RW |
|
2 |
TS1 0: TS1 handshake is enabled according to the spec, 1: TS1 detection is disabled; LTSSM will pass through relevant sub-state just after sending specified number of training sequences Default value is 0. |
RW |
|
3 |
TS2 0: TS2 handshake is enabled according to the spec, 1: TS2 detection is disabled; LTSSM will pass through relevant sub-state just after sending specified number of training sequences Default value is 0. |
RW |
|
4 |
Idle 0: Logical Idle handshake is enabled, 1: Logical Idle handshake is disabled; LTSSM will jump over relevant sub-state. Default value is 0. |
RW |
|
5 |
BRE (Block Recovery Entry) 0: Normal Operation 1: When in U0, LTSSM will not respond to any TS1 received from other party and remains in U0. Default value is 0. |
RW |
|
6 |
RTW (Remove Termination on Warm reset) 0: Normal Operation 1: LTSSM will remove Rx termination upon receiving Warm Reset LFPS signaling. Default value is 0. |
RW |
|
7 |
U3EX (U3 Exit) 0: U3 Exit handshake works normally 1: Use controlled behavior for U3 Exit response (Refer to LTSSM_U3EXIT_CONTROL). |
RW |
|
8 |
HRST This bit just affects Device mode. 0: Device will pass HotReset.Active fast just by sending minimum required TS2s with Reset bit asserted. 1: Device will remain in HotReset.Active and continue sending TS2s with Reset bit asserted till the timeout specified by LTSSM_HOTRESET_TIME expires. |
RW |
|
9 |
RxDET This bit enables controlled behavior in RxDetect state. 0: RxDetect works normally according to the spec. 1: Use controlled behavior for RxDetect (Refer to LTSSM_RXDETECT_CONTROL) |
RW |
|
31:10 |
Reserved, filled by 0 |
RO |
LTSSM_U3EXIT_CONTROL
(Offset in the Register Area: 0x0214)
Contains U3 Exit controlled behavior parameters; Denial Count and Delay Time. Values specified by this register are used when U3EX bit of LTSSM_SETTING register is set to 1. Delay time specified in this register is in terms of 8ns.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Reserved |
Deny Count |
Delay Time |
|||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Delay Time |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
23:0 |
Delay Time This is the wait time before answering to a detected U3.Exit LFPS input. Instead of starting LFPS handshake as soon as U3.Exit detected (in U3 state), BE will wait first for the specified time and then starts sending LFPS in response. Value specified is the number of 8ns periods. Default value is 0x000000. |
RW |
|
27:24 |
Deny Count This is the number of U3.Exit trials that should be ignored before sending handshake. As a U3 exit follower, BE will ignore this number of detected 10ms U3.Exit LFPS signals before replying to next U3.Exit LFPS. Default value is 0x0. |
RW |
|
31:28 |
Reserved, filled by 0 |
RO |
LTSSM_HOTRESET_TIME
(Offset in the Register Area: 0x0218)
Determines the time to stay in HotReset.Active sub-states regardless of received pattern, if bit #8 of the LTSSM_SETTING register is set. Specified with 8ns granularity.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Reserved |
HotReset Time |
||||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
HotReset Time |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
27:0 |
HotReset Time Time of staying in HotReset.Active when the HotReset fast exit is disabled (Refer to
Default value is 0x96, equal to 1.2 us. |
RW |
|
31:28 |
Reserved, filled by 0 |
RO |
LTSSM_RXDETECT_CONTROL
(Offset in the Register Area: 0x021C)
Contains RxDetect controlled behavior settings. LTSSM can repeat RxDetect.ActiveRxDetect.Quiet loop for requested times even if far-end receiver termination detected. Delay time in RxDetect.Quiet can be set through this register. Takes effect if corresponding bit (RxDET) in LTSSM_SETTING is set.
Note: Passing to Polling.LFPS from RxDetect.Active depends on the result of last termination detection in the loop. If far-end termination does not exist during last repeat time, LTSSM will not go to Polling and will stay in RxDetect according to the spec. In other words, this repeat time is the minimum number of repeating RxDetect.Active, not the maximum times.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Repeat Count |
RxDetect Quiet Time |
||||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
RxDetect Quiet Time |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
23:0 |
RxDetect.Quiet Time Time of staying in RxDetect.Quiet when the RxDetect controlled behavior is enabled (Refer to
Default value is 0x16E360 |
RW |
|
31:24 |
Repeat Count Number of RxDetect.ActiveRxDetect.Quiet loop repeat. Default value is 1 |
RW |
Generate LFPS Command
(Offset in the Register Area: 0x0340)
Manually orders any kind of LFPS signals. SW can take the control of Tx line from LTSSM and exerciser engine and order any kind of LFPS signal or EI using this register. Also reports the completion of recent request.
To generate one Ping.LFPS signal, write the value of 0x00010201 into this register.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Reserved |
Count |
||||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Type |
Reserved |
DONE |
RUN |
||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
0 |
RUN This bit should be set to start a command. It will be automatically cleared when the requested signal is completely generated. For continuous types, it will not be cleared automatically and SW should clear it for stopping requested command. |
RW |
|
1 |
DONE This bit is set by the BE whenever generating requested command is completed. |
RO |
|
7:2 |
Reserved, filled by 0. |
RO |
|
15:8 |
Type 0x01: Polling LFPS 0x02: Ping LFPS 0x04: Warm Reset 0x08: U1 Exit 0x10: U2 Exit 0x20: U3 Exit 0x40: Continuous LFPS 0x80: Continuous Electrical Idle |
RW |
|
23:16 |
Count Number of times that requested signal should be generated. It’s applicable just for Polling.LFPS and Ping.LFPS types. |
RW |
|
31:24 |
Reserved, filled by 0. |
RO |
LFPS_SCD_TREPEAT_0
(Offset in the Register Area: 0x0324)
Through this register, TRepeat of SCD Logic ‘0’ could be set to a user-defined value or spec default value.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Auto |
Duration |
||||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Duration |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
30:0 |
Duration Time specified in 8 ns granularity. Each unit is equal to 8 ns. |
RW |
|
31 |
AUTO 0: The time specified in Duration should be used as the corresponding parameter. 1: Use the spec value for corresponding parameter. Default value is 1. |
RW |
LFPS_SCD_TREPEAT_1
(Offset in the Register Area: 0x0328)
Through this register, TRepeat of SCD Logic ‘1’ could be set to a user-defined value or spec default value.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Auto |
Duration |
||||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Duration |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
30:0 |
Duration Time specified in 8 ns granularity. Each unit is equal to 8 ns. |
RW |
|
31 |
AUTO 0: The time specified in Duration should be used as the corresponding parameter. 1: Use the spec value for corresponding parameter. Default value is 1. |
RW |
LFPS_PWM
(Offset in the Register Area: 0x032C)
Through this register, TPWM of LBPS could be set to a user-defined value or spec default value.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Auto |
Duration |
||||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Duration |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
30:0 |
Duration Time specified in 8 ns granularity. Each unit is equal to 8 ns. |
RW |
|
31 |
AUTO 0: The time specified in Duration should be used as the corresponding parameter. 1: Use the spec value for corresponding parameter. Default value is 1. |
RW |
LFPS_LBPM_Logic_0
(Offset in the Register Area: 0x0330)
Through this register, TBurst of LBPS Logic ‘0’could be set to a user-defined value or spec default value.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Auto |
Duration |
||||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Duration |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
30:0 |
Duration Time specified in 8 ns granularity. Each unit is equal to 8 ns. |
RW |
|
31 |
AUTO 0: The time specified in Duration should be used as the corresponding parameter. 1: Use the spec value for corresponding parameter. Default value is 1. |
RW |
LFPS_LBPM_Logic_1
(Offset in the Register Area: 0x0334)
Through this register, TBurst of LBPS Logic ‘1’ can be set to a user-defined value or spec default value.
|
MSB |
|
|
|
|
|
|
|
|
|
|
|
|
LSB |
||
|
Auto |
Duration |
||||||||||||||
|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
Duration |
|||||||||||||||
|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
Bit Location |
Register Description |
Attributes |
|
30:0 |
Duration Time specified in 8 ns granularity. Each unit is equal to 8 ns. |
RW |
|
31 |
AUTO 0: The time specified in Duration should be used as the corresponding parameter. 1: Use the spec value for corresponding parameter. Default value is 1. |
RW |
ISO_Throughput_Support
(Offset in the Register Area: 0x0344)
Controls the isochronous transfer’s mode support for large payloads. Used only during isochronous IN and isochronous OUT transactions for throughput tests.
|
MSB |
|
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|
|
|
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|
|
|
|
LSB |
|||
|
|
OUT |
IN |
Reserved |
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|
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
|
|
Reserved |
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|
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Bit Location |
Register Description |
Attributes |
|
28:0 |
Reserved, filled by 0 |
RW |
|
29 |
This bit should be written to “1” when initiating isochronous IN transaction with 20Mb payload for throughput test |
RW |
|
30 |
This bit should be written to “1” when initiating isochronous OUT transaction with 20Mb payload for throughput test |
RW
|
|
31 |
Reserved, filled by 0 |
RW |